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ECE 204 – Digital Logic Design (4)
Design, minimize, and simulate combinational and sequential circuits using a Hardware Description Language (HDL). Develop simulation and hardware implementations, utilizing Field Programable Gate Arrays (FPGA), for logic designs within the course. This course may be subject to Enforced Prerequisites that restrict registration into the course. Check the offerings below for more information.
For more information, contact OSU Ecampus at 800-667-1465 (option 1) or ecampus.ess@oregonstate.edu.
Continue to Registration.
| Term | CRN | Sec | Cr | P/N | Instructor | Type | Status | Cap | Avail | WL Cap | WL Avail |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Sp26 | 61246 | 400 | 4 | Heer, D. | Online | Open | 75 | 75 | 0 | 0 | |
| Registration Restrictions Enforced Prereqs: (MTH 231 [C] or MTH 231H [C] ) or (MTH 251Z [C] or MTH 251HZ [C] or MTH 251 [C] or MTH 251H [C] ) Major Restrictions: +039 (Electrical and Computer Engineering) Campus Restrictions: -C (Corv) College Limitations: +16 (Engr) | |||||||||||
| Class Notes: Campus restrictions end Monday of Week 10This course requires online proctored testing, which mayinclude testing fees and the use of security measures,such as a scan of your testing environment and the requiredinstallation of a desktop application. Please carefullyreview online proctored test information at: | |||||||||||
| Syllabus: Available in Canvas to students enrolled in this course. Or contact instructor to request syllabus. (Note: An ONID account is required to view OSU's online directory.) | |||||||||||
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Academic calendar
See academic calendar for our quarter term schedule.
Winter term starts Jan. 5, 2026.
Spring term starts March 30, 2026.