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College of Engineering

CS 472 – Computer Architecture (4)

Computer architecture using processors, memories, and I/O devices as building blocks. Issues involved in the design of instruction set architecture, processor, pipelining and memory organization. Design philosophies and trade-offs involved in Reduced Instruction Set Computer (RISC) architectures. CROSSLISTED as CS 472/ECE 472. This course may be subject to Enforced Prerequisites that restrict registration into the course. Check the offerings below for more information.

For more information, contact OSU Ecampus at 800-667-1465 (option 1) or ecampus.ess@oregonstate.edu.

Continue to Registration.

TermCRNSecCrP/NInstructorTypeStatusCapAvailWL CapWL Avail
W26409724004StaffOnline Open252500
Registration Restrictions
Enforced Prereqs: ECE 375 [C]
Campus Restrictions: -C (Corv)
College Limitations: +16 (Engr)
Class Notes: Students in this section may be required to interact with teachers, teaching assistants, and students in other concurrent sections of this same course. Campus restrictions for this section end Monday of Week 10
Syllabus: Available in Canvas to students enrolled in this course. Computer Science syllabi may also be found on the College of Engineering Course and Syllabus List.
Find textbooks for CS 472 at the OSU Beaver Store (current term only). For questions related to course materials, contact the OSU Beaver Store.

Legend
= Signifies the course as a Baccalaureate Core Course.
= Signifies that fees may apply to the course.
+ = Include restriction.
- = Exclude restriction.
* = Prereq may be taken prior to or simultaneously with this course.