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CS 472 – Computer Architecture (4)
Computer architecture using processors, memories, and I/O devices as building blocks. Issues involved in the design of instruction set architecture, processor, pipelining and memory organization. Design philosophies and trade-offs involved in Reduced Instruction Set Computer (RISC) architectures. CROSSLISTED as CS 472/ECE 472. This course may be subject to Enforced Prerequisites that restrict registration into the course. Check the offerings below for more information.
For more information, contact OSU Ecampus at 800-667-1465 (option 1) or ecampus.ess@oregonstate.edu.
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Term | CRN | Sec | Cr | P/N | Instructor | Type | Status | Cap | Avail | WL Cap | WL Avail |
---|---|---|---|---|---|---|---|---|---|---|---|
W25 | 39403 | 400 | 4 | Chen, L. | Online | Open | 25 | 8 | 0 | 0 | |
Registration Restrictions Enforced Prereqs: ECE 375 [C] College Limitations: +16 (Engr) | |||||||||||
Class Notes: Students in this section may be required to interact with teachers, teaching assistants, and students in other concurrent sections of this same course. | |||||||||||
Syllabus: Available in Canvas to students enrolled in this course. Computer Science syllabi may also be found on the Electrical Engineering and Computer Science classes page. |
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Spring term starts March 31.
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