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ECE 472 – Computer Architecture (4)
Computer architecture using processors, memories, and I/O devices as building blocks. Issues involved in the design of instruction set architecture, processor, pipelining and memory organization. Design philosophies and trade-offs involved in Reduced Instruction Set Computer (RISC) architectures. CROSSLISTED as CS 472/ECE 472. This course may be subject to Enforced Prerequisites that restrict registration into the course. Check the offerings below for more information.
For more information, contact OSU Ecampus at 800-667-1465 (option 1) or ecampus.ess@oregonstate.edu.
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Term | CRN | Sec | Cr | P/N | Instructor | Type | Status | Cap | Avail | WL Cap | WL Avail |
---|---|---|---|---|---|---|---|---|---|---|---|
W26 | 40975 | 400 | 4 | Staff | Online | Open | 10 | 10 | 0 | 0 | |
Registration Restrictions Enforced Prereqs: ECE 375 [C] Major Restrictions: +307 (Computer Science) Campus Restrictions: +DSC (Dist. Degree Corvallis Student) College Limitations: +16 (Engr) | |||||||||||
Class Notes: Students in this section may be required to interact with teachers, teaching assistants, and students in other concurrent sections of this same course. Campus restrictions for this section extend beyond Week 10This course requires online proctored testing, which mayinclude testing fees and the use of security measures, suchas a scan of your testing environment. Please carefullyreview online proctor test information at: | |||||||||||
Syllabus: Available in Canvas to students enrolled in this course. Or contact department to request syllabus. |
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Academic calendar
Currently it's summer intersession. See academic calendar for our quarter term schedule.
Summer term starts June 23.
Fall term starts Sept. 24.