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ECE 572 – Computer Architecture (4)
Computer architecture using processors, memories, and I/O devices as building blocks. Issues involved in the design of instruction set architecture, processor, pipelining and memory organization. Design philosophies and trade-offs involved in Reduced Instruction Set Computer (RISC) architectures. CROSSLISTED as CS 572/ECE 572. This course may be subject to Enforced Prerequisites that restrict registration into the course. Check the offerings below for more information.
For more information, contact OSU Ecampus at 800-667-1465 (option 1) or ecampus.ess@oregonstate.edu.
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Term | CRN | Sec | Cr | P/N | Instructor | Type | Status | Cap | Avail | WL Cap | WL Avail |
---|---|---|---|---|---|---|---|---|---|---|---|
W25 | 39407 | 400 | 4 | Chen, L. | Online | Open | 10 | 5 | 0 | 0 | |
Registration Restrictions Recommended: ECE 375 College Limitations: +16 (Engr) Level Limitations: +02 (Graduate) | |||||||||||
Class Notes: Students in this section may be required to interact with teachers, teaching assistants, and students in other concurrent sections of this same course.Does not meet Graduate School's stand-alone requirement. | |||||||||||
Syllabus: Available in Canvas to students enrolled in this course. Or contact instructor to request syllabus. (Note: An ONID account is required to view OSU's online directory.) |
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